The present invention claims the benefit of Korean Patent Application No. P2001-38909 filed in Korea on Jun. 30, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, to a ferroelectric memory which can write data on a cell independent from amplification operation of a sense amplifier without restricted by the operation of the sense amplifier; and a method for driving the same.
2. Background of the Related Art
The ferroelectric memory, i.e., a Ferroelectric Random Access Memory (FRAM), having in general a data processing speed similar to a Dynamic Random Access Memory (DRAM), and being capable of conserving data even if the power is turned off, is paid attention as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
FIG. 1 illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material.
Referring to FIG. 1, it can be known that a polarization induced by an electric field is, not erased totally, but, a certain amount(xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) of which is remained, even if the electric field is removed owing to existence of the residual polarization(or spontaneous polarization). The xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states are corresponded to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 respectively in application to a memory.
A related art non-volatile ferroelectric memory will be explained with reference to the attached drawings. FIG. 2 illustrates a unit cell of the related art non-volatile ferroelectric memory.
Referring to FIG. 2, the unit cell of the related art non-volatile ferroelectric memory is provided with a bitline B/L formed in one direction, a wordline W/L formed in perpendicular to the bitline, a plateline P/L formed spaced from the wordline in a direction identical to the wordline, a transistor T1 having a gate connected to the wordline and a drain connected to the bitline, and a ferroelectric capacitor FC1 having a first terminal connected to a source of the transistor T1 and a second terminal connected to the plateline P/L.
The data input/output operation of the related art ferroelectric memory will be explained. FIG. 3A illustrates a timing diagram of a write mode operation of the related art ferroelectric memory, and FIG. 3B illustrates a timing diagram of a read mode operation of the related art ferroelectric memory.
In writing, when an external chip enable signal CSBpad transits from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 and, on the same time, an external write enable signal WEBpad transits from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99, the write mode is started. When address decoding is started in the write mode, a pulse applied to the wordline transits from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99 to select the cell. Thus, in a period the wordline is held xe2x80x98highxe2x80x99, the plateline has a xe2x80x98highxe2x80x99 signal applied thereto for one interval and a xe2x80x98lowxe2x80x99 signal applied thereto for the other interval in succession. And, in order to write a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 on the selected cell, a xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 signal synchronized to the write enable signal WEBpad is applied to the bitline. That is, if a xe2x80x98highxe2x80x99 signal is applied to the bitline, and a signal applied to the plateline is xe2x80x98lowxe2x80x99 in a period in which a signal applied to the wordline is in a xe2x80x98highxe2x80x99 state, a logical value xe2x80x981xe2x80x99 is written on the ferroelectric capacitor. If a xe2x80x98lowxe2x80x99 signal is applied to the bitline, and a signal applied to the plateline is xe2x80x98highxe2x80x99, a logical value xe2x80x980xe2x80x99 is written on the ferroelectric capacitor.
Then, the operation for reading the data stored in the cell will be explained.
If the chip enable signal CSBpad is transited from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 from outside of the cell, all bitlines are equalized to a xe2x80x98lowxe2x80x99 voltage by an equalizer signal before the wordline is selected. Then, after the bitlines are disabled, an address is decoded, and the decoded address transits the wordline from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99, to select the cell. A xe2x80x98highxe2x80x99 signal is applied to the plateline of the selected cell, to break a data corresponding to a logical value xe2x80x981xe2x80x99 stored in the ferroelectric memory. If a logical value xe2x80x980xe2x80x99 is in storage in the ferroelectric memory, a data corresponding to the logical value xe2x80x980xe2x80x99 is not broken. The data not broken and the data broken thus provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99. That is, the case of the data broken is a case when the value is changed from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop in FIG. 1, and the case of the data not broken is a case when the value is changed from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop in FIG. 1. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value xe2x80x981xe2x80x99 is provided as amplified, and in the case of the data not broken, a logical value xe2x80x980xe2x80x99 is provided as amplified. After the sense amplifier amplifies data thus, since an original data should be restored, the plateline is disabled from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 in a state a xe2x80x98highxe2x80x99 signal is applied to the wordline.
The following method may be used as one of methods for driving the related art ferroelectric memory.
A memory cell array is divided into a plurality of sub-cell arrays, and a selection switch signal SBSW is used. In a double pulse operation, a first pulse restores, or rewrites a cell data, a second pulse restores, or rewrites a logical xe2x80x9c1xe2x80x9d, i.e., a high data, broken by the first pulse, or to be written newly. In the meantime, an SBPD signal is used for reinforcing a logical xe2x80x9c0xe2x80x9d, i.e., a low data. That is, in the related art, after the operation of the sense amplifier is made by using the low data on the bitline, the low data is written again on the cell.
However, the aforementioned related art ferroelectric memory has the following problems.
The small design rule and cell size cause many difficulties in fabrication of the cell array and the peripherals, particularly, the use of poly related bitline which has a high resistance makes this problem more severe. High bitline resistance and bitline capacitance, when a ratio of Cb/CS (Cb: bitline capacitance, Cs: cell charge) is great, limits a cell size. In this case, a cell array efficiency is poor, resulting in a larger chip size. Moreover, in writing a low data, because the data is written again after the operation of the sense amplifier in which the low data on the bitline is used is finished, data writing can not be made during the operation of the sense amplifier, that increases a cell operation time period, and a cycle time period.
Accordingly, the present invention is directed to a ferroelectric memory and a method for driving the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a ferroelectric memory and a method for driving the same, which permits to write a data on a cell independent from an amplification operation of a sense amplifier without limited by the operation of the sense amplifier.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a ferroelectric memory device includes a cell array block having a plurality of sub-cell array blocks regularly arranged in columns and rows, each sub-cell array block includes a plurality of unit cells, a plurality of main bitlines disposed along a first direction corresponding to the sub-cell array blocks in column units, a plurality of sub-bitlines disposed along the first direction in a one-to-one correspondence to the sub-cell array blocks, a plurality of pairs of sub-bitline pull down signal application lines and sub-bitline enable switch signal application lines disposed along a second direction perpendicular to the first direction, each pair corresponding to the sub-cell array block for applying a sub-bitline enable switch signal and a sub-bitline pull down signal, and a plurality of switching control blocks, each corresponding to the sub-cell array block for one of enabling the sub-bitlines selectively in response to the sub-bitline enable switch signal and pulling down the sub-bitlines in response to the sub-bitline pull down signal.
In other aspect of the present invention, a ferroelectric memory device includes a cell array block having a plurality of sub-cell array blocks, each with a plurality of unit cells regularly arranged in a column direction, and a row direction, a plurality of main bitlines disposed in a first direction, a plurality of sub-bitlines disposed in the first direction, each corresponding to one of the sub-cell array blocks, a plurality of pairs of split wordlines within each of the sub-cell array blocks disposed along a second direction perpendicular to the first direction, a plurality of sub-bitline pull down application lines and sub-bitline enable switch application lines disposed along the second direction, each corresponding to the sub-cell array block, and a plurality of switching control blocks, each disposed corresponding to one of the sub-bitline pull down signal application lines and one of the sub-bitline enable switch signal application lines, and a space between adjacent sub-cell arrays, for switching a sub-bitline pull down signal, and a sub-bitline enable switch signal.
In another aspect of the present invention, a ferroelectric memory device includes a cell array block having sub-cell array blocks each with a plurality of unit cells arranged in a column direction, and a row direction regularly, a split wordline driver disposed at a center of the sub-cell array blocks divided in column units, a plurality of main bitlines running in one direction, a plurality of sub-bitlines each in correspondence to a sub-cell array block running in a direction the same with the main bitlines, a plurality of pairs of split wordlines in each of the sub-cell array blocks running in a direction perpendicular both to the main bitlines and sub-bitlines, a plurality of sub-bitline pull down signal application lines, and a plurality of sub-bitline enable switch application lines disposed along a direction the same with the split wordlines each in correspondence to the sub-cell array block, and a plurality of switching control blocks each disposed in correspondence to the sub-bitline pull down application line, and the sub-bitline enable switch application line, and a space between adjacent sub-cell arrays, for switching a sub-bitline pull down signal and a sub-bitline enable switch signal.
In another aspect of the present invention, a ferroelectric memory device includes a cell array block having sub-cell array blocks each with a plurality of unit cells arranged in a column direction, and a row direction regularly, a plurality of main bitlines disposed along one direction, a plurality of sub-bitlines each in correspondence to a sub-cell array block running in a direction the same with the main bitlines, a plurality of pairs of wordlines/platelines in each of the sub-cell array blocks running in a direction perpendicular both to the main bitlines and the sub-bitlines, a plurality of sub-bitline pull down signal application lines, and sub-bitline enable switch signal application lines running in a direction the same with pairs of the wordlines/platelines each disposed in correspondence to the sub-cell array block, and a plurality of switching control blocks each disposed in correspondence to the sub-bitline pull down signal application lines, and the sub-bitline enable switch signal application line, and a space between adjacent sub-cell arrays, for switching a sub-bitline pull down signal and a sub-bitline enable switch signal.
In another aspect of the present invention, a method for driving a ferroelectric memory of a split wordline structure for enabling, and pulling down a sub-bitline selected in response to a sub-bitline enable signal and a sub-bitline pull down signal, includes (a) enabling a first split wordline application signal to high in xe2x80x98Bxe2x80x99, xe2x80x98Cxe2x80x99, xe2x80x98Dxe2x80x99, and xe2x80x98Exe2x80x99 periods, and a second split wordline application signal to high in xe2x80x98Bxe2x80x99, xe2x80x98Cxe2x80x99, xe2x80x98Dxe2x80x99, and xe2x80x98Fxe2x80x99 periods, within a continuous enable cycle divided into xe2x80x98Axe2x80x99, xe2x80x98Bxe2x80x99, xe2x80x98Cxe2x80x99, xe2x80x98Dxe2x80x99, xe2x80x98Exe2x80x99, and xe2x80x98Fxe2x80x99 periods, (b) enabling a sub-bitline enable switch signal to high in xe2x80x98Bxe2x80x99 period at first for applying a cell data value to a bitline through a sub-bitline, disabling the sub-bitline enable switch signal to low in xe2x80x98Cxe2x80x99, and xe2x80x98Dxe2x80x99 periods for cutting off signal flows on the sub-bitline and the bitline, and enabling the sub-bitline enable switch signal to high again in xe2x80x98Exe2x80x99, and xe2x80x98Fxe2x80x99 periods for the second time for restoring, or re-writing a logical xe2x80x981xe2x80x99, i.e., a high data, broken in xe2x80x98Bxe2x80x99 period, or to be written newly, and (c) writing a logical xe2x80x980xe2x80x99, i.e., a low data, by using the sub-bitline pull down signal which is enabled to high only in xe2x80x98Cxe2x80x99, and xe2x80x98Dxe2x80x99 periods, regardless of operation of a sense amplifier.
In another aspect of the present invention, A method for driving a ferroelectric memory of a split wordline structure for enabling, and pulling down a sub-bitline selected in response to a sub-bitline enable signal and a sub-bitline pull down signal includes (a) enabling a wordline application signal to high in xe2x80x98Bxe2x80x99, xe2x80x98Cxe2x80x99, xe2x80x98Dxe2x80x99, and xe2x80x98Exe2x80x99 periods, and a plateline application signal to high in xe2x80x98Bxe2x80x99, xe2x80x98Cxe2x80x99, and xe2x80x98Dxe2x80x99 periods, within a continuous enable cycle divided into xe2x80x98Axe2x80x99, xe2x80x98Bxe2x80x99, xe2x80x98Cxe2x80x99, xe2x80x98Dxe2x80x99, xe2x80x98Exe2x80x99, and xe2x80x98Fxe2x80x99 periods, (b) enabling a sub-bitline enable switch signal to high in xe2x80x98Bxe2x80x99 period at first for applying a cell data value to a bitline through a sub-bitline, disabling the sub-bitline enable switch signal to low in xe2x80x98Cxe2x80x99, and xe2x80x98Dxe2x80x99 periods for cutting off signal flows on the sub-bitline, and the bitline, and enabling the sub-bitline enable switch signal to high again in xe2x80x98Exe2x80x99, and xe2x80x98Fxe2x80x99 periods for the second time for restoring, or re-writing a logical xe2x80x981xe2x80x99, i.e., a high data, broken in xe2x80x98Bxe2x80x99 period, or to be written newly, and (c) writing a logical xe2x80x980xe2x80x99, i.e., a low data, by using the sub-bitline pull down signal which is enabled to high only in xe2x80x98Cxe2x80x99, and xe2x80x98Dxe2x80x99 periods, regardless of operation of a sense amplifier.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.